Search - vhdl multiplier

[VHDL-FPGA-Verilog] multi

Description: 基于CPLD/FPGA的十六位乘法器的VHDL实现-Based on CPLD/FPGA multiplier of 16 to achieve the VHDL
Platform: | Size: 696320 | Author: peter | Hits:

Description: 现代电子系统课程设计基于DDS技术利用VHDL设计并制作一个数字式移相信号发生器。（1）基本要求： a．频率范围：1Hz～4kHz，频率步进为1Hz，输出频率可预置。 b．A、B两路正弦信号输出，10位输出数据宽度 c．相位差范围为0～359°，步进为1.4°，相位差值可预置。 d．数字显示预置的频率（10进制）、相位差值。（2）发挥部分 a．修改设计，增加幅度控制电路（如可以用一乘法器控制输出幅度）。 b．输出幅度峰峰值0.1～3.0V，步距0.1V，显示预置值。 -Modern electronic system design is based on DDS technology courses use VHDL to design and produce a digital shift Signal Generator. (1) the basic requirements: a. Frequency range: 1Hz ~ 4kHz, frequency step for the 1Hz, output frequency can be preset. b. A, B two sinusoidal signal output, 10-bit output data width c. Phase difference range of 0 ~ 359 °, stepping to 1.4 °, the phase difference value can be preset. d. Figures show that the frequency of Preferences (10 M), phase difference value. (2) to play a part of a. Modify the design to increase the rate of control circuit (for example, could use a multiplier to control the output rate). b. Peak-to-peak output rate of 0.1 ~ 3.0V, step 0.1V, show preset value.
Platform: | Size: 174080 | Author: 耳边 | Hits:

[VHDL-FPGA-Verilog] multiplyingunit

Description: 其乘法器原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位-Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the left after the first and add if for 0, the left After the zero-sum in full, until the highest bit multiplicand
Platform: | Size: 137216 | Author: 张华 | Hits:

[VHDL-FPGA-Verilog] ps

Description: RS(204,188)译码器的设计异步FIFO设计伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计除法器的设计加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua domain multiplier design
Platform: | Size: 48128 | Author: 苏晓东 | Hits:

[Other] multiper

Description: 用xilinx写的vhdl乘法器。是二进制的两位乘法器。里面含有代码和电路图。-Written in VHDL using Xilinx multiplier. Binary multiplier is two. Which contains code and circuit diagrams.
Platform: | Size: 113664 | Author: 费颖 | Hits:

[VHDL-FPGA-Verilog] twice_freqencey

Description: 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
Platform: | Size: 231424 | Author: nikui | Hits:

[VHDL-FPGA-Verilog] VHDL_exmple

Description: VHDL编程一百例，包括加法器、乘法器、移位寄存器、奇偶校验器等。pdf格式的，仅供学习使用-VHDL Programming 100 cases, including the adder, multiplier, shift register, parity, etc.. pdf format, for learning to use
Platform: | Size: 6634496 | Author: 徐 | Hits:

[VHDL-FPGA-Verilog] Multi11Mulply

Description: 本程序是11位带符号位的乘法器，其中最高位为符号位(sign)，中间7位是指数部分(Exponent)，最后3位是尾数(Matissa)。表示数据的范围是-2^-63-----+2^64.该工程文件有完整的程序，以及波形,验证正确。-This procedure is the unsigned 11-bit multiplier, one of the highest for the sign bit (sign), are between 7 part Index (Exponent), the final three are mantissa (Matissa). Express the scope of the data are-2 ^-63-----+ 2 ^ 64. The project document has a complete procedures, as well as waveform, verify that the correct.
Platform: | Size: 445440 | Author: 至诚 | Hits:

[Software Engineering] mult2

Description: this the multiplier 2 module for the reed solomon encoder-this is the multiplier 2 module for the reed solomon encoder
Platform: | Size: 1024 | Author: alok | Hits:

[Software Engineering] mult4

Description: this the multiplier 4 module for the reed solomon encoder-this is the multiplier 4 module for the reed solomon encoder
Platform: | Size: 1024 | Author: alok | Hits:

[VHDL-FPGA-Verilog] freqm

Description: frequency multiplier
Platform: | Size: 83968 | Author: nattu | Hits:

[VHDL-FPGA-Verilog] multi8x8

Description: VHDL实现的8位乘法器，所有仿真全部通过-VHDL to achieve 8-bit multiplier
Platform: | Size: 250880 | Author: 张四全 | Hits:

[VHDL-FPGA-Verilog] booth

Description: 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
Platform: | Size: 1024 | Author: lixiang | Hits:

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

Description: 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度，由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK.
Platform: | Size: 208896 | Author: 何蓓 | Hits:

[VHDL-FPGA-Verilog] booth

Description: 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
Platform: | Size: 1024 | Author: gyj | Hits:

[VHDL-FPGA-Verilog] multiplier_8_bit

Description: This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.
Platform: | Size: 3072 | Author: KC.Park | Hits:

[VHDL-FPGA-Verilog] WallaceTreeMultiplier

Description: Wallace Tree Multiplier in VHDL for 4bit operation fully using structural language
Platform: | Size: 2354176 | Author: suresh | Hits:

[Other] 8-bit_multiplier

Description: 用ASM原理做二進位8-BIT乘法的乘法器，內附範例的輸入檔。-ASM to do with the principle of binary multiplication of 8-BIT multiplier, the input file containing a sample.
Platform: | Size: 1024 | Author: 沉默劍士 | Hits:

[VHDL-FPGA-Verilog] 61EDA_D721

Description: 8*8乘法器设计，和大家共享，互相学习，共同进步-8* 8 multiplier design, and for all to share and learn from each other and progress together
Platform: | Size: 29696 | Author: zhao yang | Hits:

[Other] mul

Description: 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to the median minus 1, adder operand median accuracy of the 2-fold, and the gate count required operand equal to the square. 8-bit multiplier, therefore the need for 7 and 15 adder 64 and the door
Platform: | Size: 1024 | Author: 肖毅 | Hits:

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[VHDL-FPGA-Verilog] multi

[OS program] clk

[VHDL-FPGA-Verilog] multiplyingunit

[VHDL-FPGA-Verilog] ps

[Other] multiper

[VHDL-FPGA-Verilog] twice_freqencey

[VHDL-FPGA-Verilog] VHDL_exmple

[VHDL-FPGA-Verilog] Multi11Mulply

[Software Engineering] mult2

[Software Engineering] mult4

[VHDL-FPGA-Verilog] freqm

[VHDL-FPGA-Verilog] multi8x8

[VHDL-FPGA-Verilog] booth

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

[VHDL-FPGA-Verilog] booth

[VHDL-FPGA-Verilog] multiplier_8_bit

[VHDL-FPGA-Verilog] WallaceTreeMultiplier

[Other] 8-bit_multiplier

[VHDL-FPGA-Verilog] 61EDA_D721

[Other] mul

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